LIBRARY ieee;
use IEEE.NUMERIC_STD.ALL;
 
ENTITY testbench IS
END testbench;
 
ARCHITECTURE behavior OF testbench IS 
 
	 --Component under test
    COMPONENT reentrant 
    PORT(
         inputa : IN  unsigned (31 downto 0);
         inputb : IN  unsigned (31 downto 0);
         output : OUT unsigned (31 downto 0)
        );
    END COMPONENT; 

   --Inputs
	signal pix1a,pix2a,pix3a,pix4a : unsigned(7 downto 0):= (others => '0');
	signal pix1b,pix2b,pix3b,pix4b : unsigned(7 downto 0):= (others => '0');
	signal inputas : unsigned(31 downto 0):= (others => '0');
   signal inputbs : unsigned(31 downto 0):= (others => '0');

 	--Outputs
	--signal sad1,sad2,sad3,sad4 : unsigned(7 downto 0);
   signal outputs : unsigned(31 downto 0);

 
BEGIN
	--default values
	pix1a <= "01010101";
	pix1b <= "01110111";
	pix2a <= "01110111";
	pix2b <= "01010101";	 
	pix3a <= "00010111";
	pix3b <= "00010101";	
	pix4a <= "11111111";
	pix4b <= "11111111";		
	
	--map values
	inputas (31 downto 24) <= pix1a;
	inputas (23 downto 16) <= pix2a;
	inputas (15 downto 8) <= pix3a;
	inputas (7 downto 0) <= pix4a;	
	inputbs (31 downto 24) <= pix1b;
	inputbs (23 downto 16) <= pix2b;
	inputbs (15 downto 8) <= pix3b;
	inputbs (7 downto 0) <= pix4b;	
	--sad1<=outputs (31 downto 24);
	--sad2<=outputs (23 downto 16);
	--sad3<=outputs (15 downto 8); 
	--sad4<=outputs (7 downto 0);		
	
	-- Instantiate the Unit Under Test (UUT)
   uut: reentrant PORT MAP (
			    inputa => inputas,
          inputb => inputbs, 
          output => outputs
        );
	
END;
